1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to an improved semiconductor memory device and a method for manufacturing the same which incorporates therein wirings for voltage supply such as a jumping wiring.
2. Description of Related Arts
A lot of demands, high density integration, multifunction, low power consumption or the like, has been made to a large scale integration (LSI) device.
To realize the demands, it has been required to form a more precise and finer circuit pattern. Not only to comply with the above demands but also to realize a high speed operation is a very important factor to a semiconductor memory device among LSIs such as a dynamic random access memory (DRAM). Accordingly, product developing activities accompanying a variety of improvements have been made to the semiconductor memory device with reference to designing for a circuit pattern or choosing material for wiring to satisfy those demands.
It is well known that a memory cell of DRAM is, for example, constituted of a transistor and a capacitor. Contents stored in the memory cell are read out by applying a voltage to a gate electrode wiring to vary a voltage of a gate electrode, which causes to drive the transistor. Informations designated as "1" or "0" are read out by transferring charges stored in the capacitor, which is connected with the transistor, to a bit line.
As described above, DRAM is controlled in such a manner that the voltage of the gate electrode arrives at the supply voltage by supplying a voltage to the gate electrode wiring. However, with accompanied by the high density integration and the large scale capacity, there arises a problem that a voltage which is supplied to the gate electrode wiring may take long time to come to the supplied level of voltage in each of the gate electrodes, which causes short of an operational speed. To avoid the problem, there has been utilized a jumping wiring, a low resistivity wiring for applying a voltage to the gate electrode wiring, which is electrically connected with the gate electrode wiring through a contact pattern located outside of a memory cell pattern region in which the memory cell is formed, whereby the time required for settling voltages at each gate electrodes to the applied voltage can be shorten.
In a conventional semiconductor memory device which employs the jumping wiring, there exist resistance on the gate electrode wiring and parasitic capacitance on the gate electrode in an element region of the gate electrode wiring so that a time (hereinafter called as a rising time for a gate electrode) is required from when a voltage is applied to the gate electrode wiring until when the voltage of the gate electrode arrives at the voltage applied.
Further, in such a semiconductor memory device, a gate electrode itself of one memory cell among gate electrode wirings serves concurrently as a wiring for applying a voltage to a gate electrode of the adjacent memory cell. Therefore, if each of the gate electrodes respectively requires its rising time, it may take time from when one gate electrode rises until when an adjacent gate electrode rises, which is called as a delay of the rising time between gate electrodes. As a result of the accumulated delays, a large amount of delay may be generated from when a voltage is applied to one gate electrode wiring until when gate electrodes of the entire memory cells which jointly own the gate electrode wiring rise. This delay is a big problem to be solved without fail in such a semiconductor memory device.
As described above, the conventional semiconductor memory device, even though it incorporates a jumping wiring therein, has not achieved a high operational speed sufficintly enough as compared to, for example, a logic LSI. Accordingly, it has been highly requested to accelerate further the operational speed of the semiconductor memory device by shortening the rising time of the gate electrode and reducing the delay of the rising times between each gate electrodes.